Inventive concepts relate to a method of fabricating semiconductor memory devices, and more particularly, to a method of fabricating semiconductor memory devices in which a capacitor is formed in a cell array region and a signal transmission conductive layer (also referred to herein as an interconnect layer or interconnect pattern) is formed in core and peripheral regions (also referred to herein as peripheral regions).
A semiconductor memory device may be divided into a cell array region and a core/peripheral region (also referred to herein, simply, as “peripheral region”). Memory cells may be formed in an array, such as a crosspoint matrix, for example. Circuit elements that route data between memory cells and external circuit elements may be formed in regions referred to as peripheral or core regions. Differences in functionality and structure between regular arrays of memory cells and the potentially more complex peripheral circuitry can complicate the process of forming memory cells and peripheral circuitry on the same integrated circuit, particularly as integrated circuit memories become more complex and compact. A process that simplifies the formation of integrated circuit memory cells would, therefore, be highly desirable.